1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to a tester providing flexible real time test branching in both analog and digital channels.
2. Description of Related Art
An integrated circuit (IC) tester may include both digital and analog channels. Each digital channel may either supply a digital test signal input to an IC under test or sample an IC output signal to determine whether it is of an expected state. Each analog channel may either supply an analog test signal input to the IC or may digitize an IC output signal to produce a representative waveform data sequence.
The digital portion of a test is organized into a succession of test cycles. Before the start of each test cycle a pattern generator supplies a vector (a data value) to each digital channel to tell the channel what to do during the test cycle. If the channel is to supply a test signal input to the IC, the vector tells the channel how and when to change the state of the test signal during the test cycle. If the channel is to sample an IC output signal during the test cycle, the vector tells the channel when during the test cycle to sample the IC output signal and also indicates an expected state of the IC output signal. Upon sampling an IC output signal, the channel determines whether the sampled IC output signal is of the expected state. If not, the channel asserts an output FAIL signal to indicate that the IC is defective. Typically a central processor monitors the FAIL signal output of each channel and logs the IC as defective when any channel produces a FAIL signal during the test. A FAIL signal produced by any one channel is sometimes also delivered to all other channels to tell them to immediately terminate the test and to await a START signal telling them to begin testing another IC. The sequence of digital test activities performed at each IC pin during a test is therefore completely predetermined by the sequence of vectors the pattern generators are programmed to supply to the tester's digital channels. During the test the only event that can affect the course of the test is the detection by a channel of an IC failure, and the only effect a failure detection can have on the test is to terminate it early.
An analog channel may include a waveform generator that may be programmed to supply a particular analog waveform as a test signal input to an IC pin, a digitizer that may be programmed to digitize an analog output signal at some particular rate, and an acquisition memory for storing the data sequence. An analog channel typically counts cycles of a clock signal marking test cycles and may be programmed to start or stop waveform generation or digitization when the count reaches various levels. However the activities carried out by an analog channel during a test are predetermined by the manner in which it is programmed and are not affected by test results.
An IC tester may have both digital and analog channels because some ICs include both analog and digital terminals. For example a digital-to-analog converter (DAC) converts an input digital waveform sequence into an output analog signal. To test an 8-bit DAC, we could use eight digital channels to supply an 8-bit waveform data input to the DAC and one digital channel to supply a clock signal to clock the 8-bit data into the DAC. We could employ one analog channel to digitize the DAC's analog output signal, thereby to produce a data sequence that can be analyzed. Analog channels sometimes include digital signal processors for analyzing the data they acquire. Suppose we want to test a DAC to determine the highest output signal frequency it can accurately produce. One way to do that is to program the tester to repeatedly test the DAC at increasingly higher frequencies until it arrives at a frequency for which the DAC's output signal fails meet expectations. However to determine the DAC's highest operating frequency with a high degree of resolution can require a large number of test repetitions.
It is possible to reduce the number of test repetitions by carefully selecting the sampling rate after each repetition. For example during a first repetition of the test the sampling rate may be set to a mid range value. If the DAC passes the first repetition, the test frequency for a second test repetition is increased by one fourth of its full range value. If the DAC fails the first repetition of the test, the test frequency for the second repetition is decreased by one fourth of its full range value. For the third repetition, the test frequency is increased or decreased by one eighth of its full range value depending on the pass/fail result of the second repetition. When the process is continued, with increasingly smaller adjustments to the test frequency for each successive repetition, the tester can quickly zero in on the DAC's highest frequency in a relatively few test repetitions. One problem with this method, however, is that it requires a host computer to reprogram the tester before each test repetition in order to set the test frequency based on test results of the preceding repetition. The need to reprogram and restart the tester channels for each test repetition can greatly lengthen the test process.
What is needed is an integrated circuit tester having digital and analog channels for carrying out a test on an IC that may conditionally branch at various points during the test depending on previous test results. Such channels could perform a sequence of test repetitions in which parameters of each test repetition are set depending on the results of a preceding test repetition without having to be stopped, reprogrammed, and restarted after each test repetition.